Optimizing Test Speed to reduce Test Costs for SiC/GaN Power Devices

Testing SiC and GaN power semiconductors is a major manufacturing cost factor. This presentation explains how test costs are structured and which levers can reduce them, with a focus on test speed. Hardware measures include suitable bus systems and self-optimizing pulse patterns. The main potential, however, lies in the test-system software architecture. A multithreaded approach combines resource management, path finding, parameter handling and the test program. Alexander Loibl introduces this architecture, explains the factors affecting test speed and uses a practical example to show how test time is distributed and where optimization is possible.