Lecture
Session Risc-5: Levelling up next generation SDV by using RISC-V
- 13.11.2024 at 12:30 - 12:50
- Smart Mobility Stage (B6.452)
- Language: English
- Type: Lecture
Lecture description
Moving to SDV and centralized E/E architectures is the next key milestone in Automotive Electronics. But today's widely used distributed and fragmented E/E architectures are not suited for that evolutionary next step. Instead of a fast adoption of 'software first', highly complex virtualization layers and containers are needed making the handling of SDV even more complex, expensive and difficult-to-realize.
To support a real move to SDV architectures, the industry will need a much more simplified and fit-for-purpose hardware than ever before. We are seeing several layers of simplifications which are needed to enable the evolution towards real SDV.
The current distributed systems are complex-by-default and hence increase complexity exponentially. On top of this, the hardware is very fragmented. Incompatibilities are everywhere.
Major steps towards simplification are hence the move to HPC and zonal ECU's. Obviously, the faster and radical the change, the better. To stop fragmentation on the hardware side, a move to open standards and unified instruction sets seem to be logical. The more unified the hardware is, the less of an abstraction is needed. The logical other key simplification is to move to a unified IP landscape as much as possible.
Using RISC-V throughout the major system components enables designers a completely new level of software architecture. The RISC-V based move to HPC and Zonal Architecture promises a radically simplified approach while providing a powerful and especially unified architecture.
By developing a complete portfolio from small ASIC's, to Zonal MCU's up to HPC parallel coherent high-performance cores and a new integration approach for NPU's, SiFive is enabling a radically simplified SDV architecture unifying the ISA and relevant system peripherals across the entire platform
To support a real move to SDV architectures, the industry will need a much more simplified and fit-for-purpose hardware than ever before. We are seeing several layers of simplifications which are needed to enable the evolution towards real SDV.
The current distributed systems are complex-by-default and hence increase complexity exponentially. On top of this, the hardware is very fragmented. Incompatibilities are everywhere.
Major steps towards simplification are hence the move to HPC and zonal ECU's. Obviously, the faster and radical the change, the better. To stop fragmentation on the hardware side, a move to open standards and unified instruction sets seem to be logical. The more unified the hardware is, the less of an abstraction is needed. The logical other key simplification is to move to a unified IP landscape as much as possible.
Using RISC-V throughout the major system components enables designers a completely new level of software architecture. The RISC-V based move to HPC and Zonal Architecture promises a radically simplified approach while providing a powerful and especially unified architecture.
By developing a complete portfolio from small ASIC's, to Zonal MCU's up to HPC parallel coherent high-performance cores and a new integration approach for NPU's, SiFive is enabling a radically simplified SDV architecture unifying the ISA and relevant system peripherals across the entire platform
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