(EF14-8) Multi-instance machine learning models on limited hardware resources

Presented by Bartosz Boryna, Senior Application Engineer, STMicroelectronics

Implementing machine learning (ML) algorithms on limited-resource microcontrollers, such as microcontrollers based on the entry-level Arm Cortex®-M0+ core for instance, is challenging. Indeed, the need to allocate relevant RAM and flash memory and to execute the ML model impacts real-time constraints. The efficiency of algorithm implementation is crucial in such cases. An ML model is often not flexible enough to handle a wide range of environmental variations, and increasing the model's complexity further strains hardware resources, making implementation impractical, especially on entry-level microcontrollers. Our multi-instance ML models approach leverages the synergy of interactions among low-footprint models. They focus on simple tasks, enabling the implementation of complex ML scenarios, such as a binary classifier (anomaly detector) triggering an n-class classifier. We considered efficient algorithm coding approaches and solutions to accelerate development. In this session, we will present the results from our lab use cases and discuss resource usage and software architecture.