Why MIMO requires FinFET and what challenges an RF system engineer will need to overcome
In the presentation I outline why FinFET design is essential in delivering MIMO systems, showing that while drawbacks do exist they can be overcome, explaining the key design challenges and providing rules to help analog engineers.
Background
5G terrestrial and satellite communications have already begun to use bands in the FR2 range (24~52GHz). The range of wireless communications in these bands is limited by the short signal wavelength and transceivers therefore rely on the integration of MIMO systems to meet the link budget and mitigate interference. For the ASIC designer, this means more channels, more radios, more digital signal processing.
Power consumption
FinFET is the ideal technology for large MIMO systems; by enabling ‘digital radio’ solutions, based on RF-ADCs/DACs, it gives the flexibility to design ASICs that support multiple standards. There is, however, a drawback in implanting this architecture: power consumption. Energy-per-conversion increases exponentially when operating above 1 GHz; for example, moving the sampling frequency from 1 to 5GHz, increases the converter power by 20x.
Significant power can be saved by designing an RF analog front end (AFE), converting the multi-GHz RF signal to a lower intermediate-frequency (IF) below 500MHz, before performing the transition to the digital domain and relaxing the data-converters sampling frequency.
Further benefits
Using FinFET for analog design introduces multiple benefits: devices are compact, the high Gm and Rout are ideal to design analog amplifiers, RF designers can leverage the excellent high-frequency performance, with peak fT of 600GHz.
Again, there is a drawback to this approach too: the number of masks required by the technology is 2/3 times higher than in planar geometries. The amount of design rules increases accordingly, making the technology better suited for ‘machine driven’ digital implementations. Attempts to use custom analog layout flows are bound to fail, especially when using the smaller (7nm) nodes to achieve highest system integration and lowest power consumption.
Rules to design MIMO in FinFET technology
In FinFET, making a regular analog layout is paramount for success. Any variation from this approach may give some short term advantages in the initial schematic simulations, that disappear when parasitic resistors (due to metals and VIAs) are introduced. Simulations are slow and engineers need to resort to approximations to control simulation time.
The implementation challenges are significant, but so too are the benefits. The following rules can help engineers handling the intricacies of FinFET analog design:
1. Do not mix devices having different dimensions
2. Use repeatable patterns
3. Estimate interconnect parasitics from the start
4. Use digital calibration to correct analog errors
5. Current density limits the transmitter output power
6. Corner frequency of flicker noise is high
7. Simulations are slow